A nonvolatile semiconductor memory device represented by a flash memory has been used widely in fields such as a computer, communication, a measurement instrument, an automatic control device and a living ware device used around individuals, and an inexpensive nonvolatile semiconductor memory device with a large capacity is highly required. This is mainly because the semiconductor memory device can be electrically written and has nonvolatile properties in which data is not erased even when a power supply is cut, and thereby can function as an readily portable memory card, a mobile phone and the like, or a data storage, a program storage and the like to be stored in a nonvolatile way as initial setting in a device operation.
In addition, some nonvolatile semiconductor memory devices using new materials have been disclosed recently, and a RRAM (Resistance Random Access Memory) is a promising one thereof. The RRAM fulfills its memory function by use of a variable resistance element in which a resistance thereof is changed when a current larger than a readout current is applied, and its possibility is expected because of its high potential such as a high speed, a large capacity, and low power consumption.
The following Patent Document 1 discloses a semiconductor memory device having one or more memory cell arrays in which nonvolatile memory cells each provided with a variable resistance element (resistance changing element) are arranged in a row direction and a column direction, and a plurality of word lines and a plurality of bit lines are arranged in the row direction and the column direction to select a certain memory cell or memory cell group from the above memory cells.
According to the above memory cell, one end of the variable resistance element to store information when an electric resistance thereof is changed is connected to a drain of a selective transistor, and in the memory cell array, one of the other end of the variable resistance element and a source of the selective transistor is commonly connected to the bit line in the column direction, and the other is commonly connected to a source line, and a gate of the selective transistor is commonly connected to the word line in the row direction. Erasing means is provided in such a manner that when voltages are applied to the word line, the bit line, and the source line connected in the memory cell array under a predetermined application condition, and the electric resistance of the variable resistance element in the memory cell to be erased in the memory cell array is set to a predetermined erased state, the information in the memory cell is erased. The erasing means is provided with a collective erasing mode in which all the memory cells in the memory cell array are collectively erased, and an individual erasing mode, in at least one memory cell array, so that writing speed is improved and data is efficiently used.
More specifically, since the erasing mode can be switched based on the voltage application condition such that when program data and the like are stored in the memory cells in the memory cell array and they are collectively written, the collective erasing mode is used, and when code data and the like are stored in the memory cells in the memory cell array and the code data is written individually, the individual erasing mode is used, the data can be efficiently used based on the characteristics of the data stored in the memory cells.
According to the above erasing means, all the memory cells in the memory cell array can be collectively erased when the voltage application condition is set to the collective erasing mode, in at least one memory cell array, and part of the memory cells in the memory cell array can be individually erased when the voltage application condition is set to the individual erasing mode, in at least another memory cell array, so that the collective erasing mode and the individual erasing mode can be switched with respect to each memory cell array. Thus, the memory cell array can be efficiently used based on the characteristics of the data stored in the memory cell.    Patent Document 1: Japanese Unexamined Patent Publication No. 2004-185754